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This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage VDD and threshold voltage VTH in active and standby modes. In the active mode, on the basis of delay monitoring results, either VDD control or VTH control is selected to avoid any oscillation problem between them. In VDD control, on the basis of delay monitoring results, VDD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In VTH control, on the basis of power monitoring results, VTH is adjusted so as to maintain a certain switching current ISW/leakage current ILEAK ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current ISUBTH to substrate current ISUB) is improved by taking into consideration both the effects of lowering VDD and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the ISW/ILEAK ratio in the active mode and 2) detect optimum body bias conditions (ISUBTH=ISUB) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.