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A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor

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12 Author(s)
Hwa-Joon Oh ; IBM Syst. & Technol. Group, Austin, TX, USA ; Mueller, S.M. ; Jacobi, C. ; Tran, K.D.
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The floating-point unit (FPU) in the synergistic processor element (SPE) of a CELL processor is a fully pipelined 4-way single-instruction multiple-data (SIMD) unit designed to accelerate media and data streaming with 128-bit operands. It supports 32-bit single-precision floating-point and 16-bit integer operands with two different latencies, six-cycle and seven-cycle, with 11 FO4 delay per stage. The FPU optimizes the performance of critical single-precision multiply-add operations. Since exact rounding, exceptions, and de-norm number handling are not important to multimedia applications, IEEE correctness on the single-precision floating-point numbers is sacrificed for performance and simple design. It employs fine-grained clock gating for power saving. The design has 768K transistors in 1.3 mm2, fabricated SOI in 90-nm technology. Correct operations have been observed up to 5.6 GHz with 1.4 V and 56°C, delivering 44.8 GFlops. Architecture, logic, circuits, and integration are codesigned to meet the performance, power, and area goals.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 4 )

Date of Publication:

April 2006

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