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RLC parasitic extraction and circuit model optimization for Cu/SiO2-90nm inductance structures

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1 Author(s)

An efficient interconnects modeling and optimization methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Cu/SiO2 90nm process test chip.

Published in:

Microwave Conference, 2005 European  (Volume:3 )

Date of Conference:

4-6 Oct. 2005