By Topic

Profiling Macro Data Flow Graphs for Parallel Implementation of FDTD Computations

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Smyk, A. ; Polish-Japanese Inst. of Inf. Technol., Warsaw ; Tudruj, M.

In this paper, we present methodology, which enables designing and profiling macro data flow graphs that represent computation and communication patterns for the FDTD (finite difference time domain) problem in irregular computational areas. Optimized macro dataflow graphs (MDFG) for FDTD computations are generated in three main phases: generation of initial MDFG based on wave propagation area partitioning, MDFG nodes merging with load balancing to obtain given number of macro nodes and communication optimization to minimize and balance internode data transmissions. The computation efficiency for several communication systems (MPI, RDMA RB, SHMEM) is discussed. Relations between communication optimization algorithms and overall FDTD computation efficiency are shown. Experimental results obtained by simulation are presented

Published in:

Parallel and Distributed Computing, 2005. ISPDC 2005. The 4th International Symposium on

Date of Conference:

4-6 July 2005