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A design for an FPGA-based implementation of Rijndael cipher

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3 Author(s)
Abdelhalim, M.B. ; Fac. of Eng., Cairo Univ., Giza ; Aslan, H.K. ; Farouk, H.

In this paper we propose a modified implementation of Rijndael AES encryption standard based on the fact that FPGAs include built-in memory blocks, therefore we store all the results of the fixed operations within the memory modules instead of using a dedicated hardware to implement them. An implementation proposed in http://islab.oregonstate.edu was implemented in FPGA but it didn't use the built-in memory resources effectively. Therefore, based on that design we made our modifications. Our modified design is compared with the original design and gives 11% reduction in area and 22% increase in speed (throughput). The memory used increases by 180% but this increase is not severe as it utilizes the already manufactured memory resources inside the FPGA efficiently. Then we compared our design with many published designs based on ALTERA FPGAs (P. Mroezkowski, 2000) and XILINIX FPGAs (D. Ka Yau Tong, et al., 2002). Our design gives the highest throughput and area utilization over all the iterative looping based FPGA implementations of the AES standard (D. Ka Yau Tong, et al., 2002). We implemented the decryption system of the standard and we compared this standard with the design based on ALTERA FPGAs (P. Mroezkowski, 2000) and our design gives 48% reduction in area and 79% increase in speed (throughput) but the memory usage is increased by 315%, but this increase is not severe as it utilizes the already manufactured memory resources inside the FPGA efficiently

Published in:

Information and Communications Technology, 2005. Enabling Technologies for the New Knowledge Society: ITI 3rd International Conference on

Date of Conference:

5-6 Dec. 2005