Referenced Items are not available for this document.
Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure was carried out for hp45 low standby power (LSTP) device (Lg = 25nm). GIDL is reduced by using gradual and offset source/drain (S/D) profile while degradation of drive current is minimized. Through the optimization of lateral spread and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable by FinFET with 10nm fin width
Published in:
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Date of Conference: 5-5 Dec. 2005
- Page(s):
- 980 - 983
- Print ISBN:
- 0-7803-9268-X
- INSPEC Accession Number:
- 9071928
- Conference Location :
- Washington, DC
- Digital Object Identifier :
- 10.1109/IEDM.2005.1609526
- Product Type:
- Conference Publications
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