Scaling the high-performance double-gate SOI MOSFET down to the 32 nm technology node with SiO/sub 2/-based gate stacks

We apply state-of-the-art simulation to investigate the possibility to scale the UTB-DG MOSFET using rather conventional SiO
₂
-based dielectrics with a minimum thickness of 1 nm, a lower limit set by the need for process yield and reproducibility. The analysis include short-channel effects, gate leakage tunneling current, ON-current and the intrinsic switching delay-time CV/I