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Scaling the high-performance double-gate SOI MOSFET down to the 32 nm technology node with SiO/sub 2/-based gate stacks

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4 Author(s)

We apply state-of-the-art simulation to investigate the possibility to scale the UTB-DG MOSFET using rather conventional SiO2-based dielectrics with a minimum thickness of 1 nm, a lower limit set by the need for process yield and reproducibility. The analysis include short-channel effects, gate leakage tunneling current, ON-current and the intrinsic switching delay-time CV/I

Published in:

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Date of Conference:

5-5 Dec. 2005

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