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Computational study of carbon nanotube p-i-n tunnel FETs

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3 Author(s)
Koswatta, S.O. ; Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN ; Nikonov, D.E. ; Lundstrom, M.S.

Reducing transistor leakage current by increasing the sub-threshold slope beyond the thermal limit (60mV/decade at room temperature) could alleviate the heat dissipation requirements of high-density ICs. This paper examines the potential of a carbon nanotube p-i-n tunnel FET for less than 60mV/dec operation. Both ballistic transport and transport with inelastic scattering are considered. The device performance is compared to that of a carbon nanotube n-i-n MOSFET. An extensive discussion on device optimization for p-i-n tunnel FETs is also presented

Published in:
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Date of Conference: 5-5 Dec. 2005

Page(s):
518 - 521
Print ISBN:
0-7803-9268-X
INSPEC Accession Number:
9071836
Conference Location :
Washington, DC
Digital Object Identifier :
10.1109/IEDM.2005.1609396
Product Type:
Conference Publications

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