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Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths

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18 Author(s)
Singh, D.V. ; T. J. Watson Res. Center, IBM Semicond. R&D Center, Yorktown Heights, NY ; Sleight, J.W. ; Hergenrother, J.M. ; Ren, Z.
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We report for the first time, the effect of stress memorization (SM), and the combined effects of SM and dual stress liner (DSL) on high performance fully-depleted ultra-thin channel devices with a raised source/drain architecture and channel thickness of 18nm. SM results in significant drive current and mobility enhancement, comparable to that obtained using the DSL approach. Stress transfer to the channel during SM likely occurs through the poly-gate, becoming more effective as the body is thinned. Combining SM and DSL results in a net gain that is substantially larger than that obtained using each technique separately

Published in:

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Date of Conference:

5-5 Dec. 2005