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Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations

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20 Author(s)
Yong-Sung Kim ; Adv. Technol. Dev., Samsung Electron. Co. Ltd., Gyunggi-Do ; Sang-Hyeon Lee ; Soo-Ho Shin ; Sung-Hee Han
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We integrate FinFET DRAM in sub-60nm feature size. To avoid severe passing gate effects in FinFET cell array, we introduce a local damascene gate structure. Threshold voltage control of the ultra thin body transistors is successfully achieved by adopting p+ boron in-situ doped poly-silicon gate on the FinFET cells. As a result, very stable and uniform operation of FinFET cells is realized. The local damascene FinFET with p+ gate can become a highly feasible mainstream DRAM technology for sub-60nm low-power high-speed devices

Published in:

IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

Date of Conference:

5-5 Dec. 2005