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Advanced scalable ultralow-k/Cu interconnect technology for 32 nm CMOS ULSI using self-assembled porous silica and self-aligned CoWP barrier

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20 Author(s)
Kikkawa, T. ; Nat. Inst. of Adv. Ind. Sci. & Technol., MIRAI, Tsukuba ; Chikaki, S. ; Yagi, R. ; Shimoyama, M.
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An advanced scalable Cu damascene process was developed using self-assembled porous silica with tetramethylcyclo-tetrasiloxane (TMCTS) treatment and selective electroless plating of Cu barrier. It is found that the TMCTS vapor treatment could recover process-induced damages after plasma ashing and chemical mechanical polishing, resulting in no line-width dependence of the effective dielectric constant of the porous silica films. Furthermore, the selective electroplating of CoWP on Cu interconnects could suppress Cu drift and improve time-dependent dielectric breakdown of the porous silica film

Published in:

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Date of Conference:

5-5 Dec. 2005