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45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications

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35 Author(s)
Okuno, M. ; Fujitsu Labs. Ltd., Fujitsu Ltd., Kuwana ; Okabe, K. ; Sakuma, T. ; Suzuki, K.
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We describe the integration of a 45-nm node CMOS for low operation power (LOP) application. The SD extension profile along with a strain channel and a thin-gate-SiON were optimized to keep high drive current at the 45-nm node. A novel STI structure was developed to reduce the SRAM cell size. Nano-clustering silica (NCS) without a middle-etch stopper (MES) was also developed to decrease the wire capacitance. As a result, we achieved an excellent LOP device operation with conventional processing, and we produced a 50% smaller SRAM cell-size as compared to the 65-nm node

Published in:

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Date of Conference:

5-5 Dec. 2005