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As the complexity of very large scale integration (VLSI) circuits increases, the routability problem becomes more and more important in modern VLSI design. In general, the flexibility improvement of the edges in a routing tree has been exploited to release the routing congestion and increase the routability in the routing stage. On the basis of the definition of the dynamic routing flexibility in a routing tree and the timing-constrained location flexibility of any Steiner point, an efficient assignment approach is proposed to reconstruct a timing-constrained flexibility-driven routing tree in a grid-based routing model by reassigning the feasible locations of the Steiner points in a routing tree. By using the concept of dynamic tree reconstruction, all the routing trees in a routing plane can be reconstructed tree by tree to release the possible congestion condition for timing-constrained congestion-driven global routing. The experimental results show that the proposed algorithm, TCGR_DTR, uses less time to obtain nearly 100% congestion improvement than the previously proposed algorithm, TCGR, for the tested benchmark circuits.