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Low power system on chip bus encoding scheme with crosstalk noise reduction capability

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3 Author(s)
Khan, Z. ; Sch. of Eng. & Electron., Univ. of Edinburgh, UK ; Arslan, T. ; Erdogan, A.T.

Inter-wire coupling is a major source of wire load and delay faults for on-chip buses implemented in ultra-deep submicron system on chip (SoC) systems. Elimination or minimisation of such faults is crucial to the performance and reliability of SoC designs. A novel on-chip bus encoding scheme targeting high-performance generic SoC systems is presented. In addition to its efficiency in terms of power, the scheme reduces delay faults by completely eliminating the most critical type of crosstalk coupled switched capacitance. The authors describe the technique and its implementation (using the widely adopted AMBA-AHB SoC bus standard) and provide experimental results indicating 22-36% energy saving for systems implemented in 0.18 μm CMOS technology.

Published in:

Computers and Digital Techniques, IEE Proceedings -  (Volume:153 ,  Issue: 2 )

Date of Publication:

6 March 2006

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