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Compression/scan co-design for reducing test data volume, scan-in power dissipation and test application time

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5 Author(s)
Yu Hu ; Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China ; Yin-He Han ; Xiao-wei Li ; Hua-wei Li
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Testing chips is very critical to guarantee chips are fault-free before they are integrated in a system, so as to increase the reliability of the system. Although full-scan is a widely adopted design-for-test technique for LSI design and testing, the need for reducing the test data volume, scan-in power dissipation and test application time (VPT) of the full-scan designed chip is imperative. Based on the analysis of the characteristics of the variable-to-fixed run-length coding technique and the random access scan architecture, this paper presents a novel design scheme tackling all VPT issues simultaneously. Experimental results on ISCAS'89 benchmarks have shown on average 51.2%, 99.5%, 99.3% and 85.5% reduction in test data volume, average scan-in power dissipation, peak scan-in power dissipation and test application time, respectively.

Published in:

Dependable Computing, 2005. Proceedings. 11th Pacific Rim International Symposium on

Date of Conference:

12-14 Dec. 2005