By Topic

A unified approach for verification and validation of systems and software engineering models

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
L. Alawneh ; Concordia Inst. for Inf. Syst. Eng., Concordia Univ., Montreal, Que., Canada ; M. Debbabi ; F. Hassaine ; Y. Jarraya
more authors

We present in this paper a unified paradigm for the verification and validation of software and systems engineering design models expressed in UML 2.0 or SysML. This paradigm relies on an established synergy between three salient approaches, which are model-checking, program analysis, and software engineering techniques. To illustrate the accomplishment of our results, we have designed and implemented an integrated and automated computer-aided assessment tool. We provide three case studies for sequence, state machine, and class and package diagrams to demonstrate the benefits of our methodology

Published in:

13th Annual IEEE International Symposium and Workshop on Engineering of Computer-Based Systems (ECBS'06)

Date of Conference:

27-30 March 2006