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A low phase noise 2 GHz VCO using 0.13 μm CMOS process

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4 Author(s)
Jinsung Choi ; Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol., China ; Seonghan Ryu ; Huijung Kim ; Bumman Kim

A 2 GHz LC VCO with a large improvement in phase noise is designed and implemented in 0.13μm CMOS process. It has phase noise of -100.7 dBc/Hz, -130.6 dBc/Hz, and -140.8 dBc/Hz at 100 kHz, 1 MHz, and 3 MHz offset frequencies from the carrier, respectively. The phase noise reduction of about 10 dB is observed for all controllable voltage range, as compared with a comparable conventional VCO. This VCO consumes 3.29 mA from a 1.8 V supply with the silicon area of 500 μm × 850 μm.

Published in:

Microwave Conference Proceedings, 2005. APMC 2005. Asia-Pacific Conference Proceedings  (Volume:4 )

Date of Conference:

4-7 Dec. 2005

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