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An architecture of highly parallel computer AP 1000

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5 Author(s)
Ishihata, H. ; Fujitsu Labs. Ltd., Kawasaki, Japan ; Horie, T. ; Inano, S. ; Shimizu, T.
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A highly parallel computer with distributed memory called the AP1000 has been developed. The system consists of 64 and 1024 processing elements and three independent networks called the torus network (T-net), broadcast network (B-net), and synchronization network (S-net). The design goal for the AP1000 is to attain low-latency, high-throughput communication. To reduce the overall communication latency, a message controller and a new routing scheme on the T-net have been developed. The design concepts, architecture, and some results from performance tests for the AP1000 are presented

Published in:

Communications, Computers and Signal Processing, 1991., IEEE Pacific Rim Conference on

Date of Conference:

9-10 May 1991