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A 5 GHz 2:1 static frequency divider IC was realized in a 0.25-μ mixed-signal CMOS technology with an fT of 18.6 GHz. The divider is based on a master-slave toggle flip-flop (MSTFF) of source coupled FET logic (SCFL) and a wide band output buffer. The basic circuits and layout strategies to achieve low jitter and high speed are discussed. The measured rms jitter of the output waveform is 1.38 ps at 5 GHz input. The core power dissipation is 5 mW under a 2.5V supply.