2.4 GHz divide-by-256/spl sim/271 single-ended frequency divider in standard 0.35-/spl mu/m CMOS technology

This paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 271 in standard 0.35-/spl mu/m 2P4M CMOS technology. This frequency divider is composed of a synchronous CML divide-by-4/5 prescaler, an asynchronous TSPC TFF divide-by-64 divider and digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 MHz to 2.9 GHz. Most of input sensitivity levels are about -10 dBm and the lowest level is -25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.2/spl times/0.7 mm/sup 2/.