A modified word serial bit parallel algorithm for FPGA implementation of digital ionospheric radar

Digital signal processing (DSP) has become an integral part of wireless communication systems and equivalent traditional analog systems can be developed with required fidelity at reasonable cost. In a previous work, a DSP technique is employed for radar upconversion using combinations of upsampling and narrow band FIR filtering. An efficient FPGA implementation of the DSP modulator is possible exploiting filter symmetry since symmetrical properties of word serial bits parallel (WSBP) FIR filters improve system throughput. However arithmetic processing rate for the WSBP symmetric models is higher than that of the non-symmetric models. In this paper we present a modified WSBP symmetrical algorithm to reduce the arithmetic processing for implementation of direct conversion ionospheric radar. In WSBP approach processing is performed in integers as block of bits. Matching and buffering criterion are used to reduce computations up to fifty percent. The algorithm can be extended to applications with similar characteristics particularly for system on chip (SOC) techniques.