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1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

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5 Author(s)
Staszewski, R.B. ; Wireless Analog Technol. Center, Texas Instrum. Inc., Dallas, TX, USA ; Vemulapalli, S. ; Vallur, P. ; Wallberg, J.
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We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. It additionally serves as a CMOS process strength estimator for analog circuits in this large system-on-chip. Measured integral nonlinearity is 0.7 least significant bits. The TDC consumes 5.3 mA raw and 1.3 mA with power management from a 1.3-V supply.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:53 ,  Issue: 3 )