Fault-Tolerance in Micro Programmed Control: Architectures & Schematic Synthesis

The paper deals with architectural and schematic design of concurrently (on-line) self-checking Micro Program Control Units. The checking is organised by using a special check keys added to each microinstruction. The sequence of keys appearing on the output of MPCU during the program execution is then monitored. It allows checking the control flow by comparing the actual sequence of the check keys against a reference sequence corresponding to fault-free operation of MPCU. Three main architectures discussed in the paper are: a) based on the use of Compression-in-Space of the check keys; b) based on implementation of Compression-in-Space & Compression-in-Time; and c) Compression & Generation check keys -based. The design procedure for the checking circuitry based on the use of Compression & Generation is discussed in the paper for two types of the check key generators: a standard one (for example, M-sequence generator) and an unique generator (specially synthesised sequential automata producing some required digital sequence).