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Partial and dynamic reconfiguration of FPGAs: a top down design methodology for an automatic implementation

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2 Author(s)
F. Berthelot ; CNRS UMR 6164, IETR-INSA, Rennes, France ; F. Nouvel

Dynamic and partial reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level adequation algorithm architecture process. We present a method generates automatically the design for both partially and fixed parts of FPGAs

Published in:

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)

Date of Conference:

2-3 March 2006