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On the design of VLSI arrays for discrete Fourier transform

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2 Author(s)
Liu, C.-M. ; Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Jen, C.-W.

In this paper the design of VLSI arrays for the discrete Fourier transform (DFT) is investigated through three topics: (1) algorithm exploitation, derivation and analysis, array realisation, and schemes to calculate arbitrarily long length DFT using a reasonable sized array. Four DFT systolic algorithms are examined and compared in terms of computing parallelism and computational complexity. Among the four algorithms, one is newly proposed. The new one exhibits much higher computating parallelism and lower computational complexity than the other three, but is applicable when the DFT length is prime. Based on the four algorithms, seven systolic arrays and seven two-level pipelined systolic arrays are devised. The outstanding features of these arrays are that the number of I/O channels is independent of the DFT length and the time overhead in manipulating consecutive data bundles are eliminated. Two schemes are presented to calculate long-length DFT using arrays with a reasonable number of processing elements. Performance of different algorithms, arrays and schemes is compared and summarised in six tables to serve as the selection criteria for different applications

Published in:

Circuits, Devices and Systems, IEE Proceedings G  (Volume:139 ,  Issue: 4 )