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Design methodology of CMOS low power

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3 Author(s)
Hao Dongyan ; Coll. of Inf. Sci., Zhejiang Univ., Hangzhou ; Zhang Ming ; Zheng Wei

The growing demand for portable electronic devices has led to an increased emphasis on power consumption within the IC design industry. In this article, according the design flow of VLSI, we present a survey of low power design methodology at five levels such as system, behavioral, architectural, logic and physical levels

Published in:

Industrial Technology, 2005. ICIT 2005. IEEE International Conference on

Date of Conference:

14-17 Dec. 2005