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Sequential Circuit Test Generation in a Genetic Algorithm Framework

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4 Author(s)
Rudnick, E.M. ; Center for Reliable & High-Performance Computing, University of Illinois, Urbana, IL ; Patel, J.H. ; Greenstein, G.S. ; Niermann, T.M.

Test generation using deterministic fault-oriented algorithms is highly complex and time-consuming. New approaches are needed to augment the existing techniques, both to reduce execution time and to improve fault coverage. In this work, we describe a genetic algorithm (GA) framework for sequential circuit test generation. The GA evolves candidate test vectors and sequences, using a fault simulator to compute the fitness of each candidate test. Various GA parameters are studied, including alphabet size, fitness function, generation gap, population size, and mutation rate, as well as selection and crossover schemes. High fault coverages were obtained for most of the ISCAS89 sequential benchmark circuits, and execution times were significantly lower than in a deterministic test generator in most cases.

Published in:

Design Automation, 1994. 31st Conference on

Date of Conference:

6-10 June 1994