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Formally Verifying a Microprocessor Using a Simulation Methodology

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2 Author(s)
Beatty, D.L. ; Cadence Berkeley Laboratories, Cadence Design Systems, Inc. ; Bryant, R.E.

Formal verification is becoming a useful means of validating designs. We have developed a methodology for formally verifying dataintensive circuits (e.g., processors) with sophisticated timing (e.g., pipelining) against high-level declarative specifications. Previously, formally verifying a microprocessor required the use of an automatic theorem prover, but our technique requires little more than a symbolic simulator. We have formally verified a pre-existing 16-bit CISC microprocessor circuit extracted from the fabricated layout.

Published in:

Design Automation, 1994. 31st Conference on

Date of Conference:

6-10 June 1994

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