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Design-for-Testability for Path Delay Faults in Large Combinational Circuits Using Test-Points

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2 Author(s)
Pomeranz, I. ; Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA ; Reddy, S.M.

We present a method for test-point insertion in large combinational circuits, to increase their path delay fault testability. Using an appropriate test application scheme with multiple clock periods, a test-point on a line g divides the set of paths through g for testing purposes into a subset of paths from the primary inputs up to g, and a subset of paths from g to the primary outputs. Each one of these subsets can be tested separately. The number of paths that need to be tested directly is thus reduced. Test-point insertion is done to reduce the number of paths, using a time-efficient procedure. Indirectly, it also reduces the number of tests and renders untestable paths testable. Experimental results are presented to demonstrate the effectiveness of the method proposed in increasing the testability of large benchmark circuits, and to demonstrate the overheads involved.

Published in:

Design Automation, 1994. 31st Conference on

Date of Conference:

6-10 June 1994