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We introduce a new approach for optimizing clock tree, especially for high-speed circuits. Our approach provides a useful guideline to a designer; by user-specified parameters, design favors will be satisfied. Three of these tradeoffs will be provided in this paper. 1) First, to provide a "good" tradeoff between skew and wirelength, a new clock tree routing scheme is proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and minimum rectilinear Steiner tree. 2) When a clock tree construction scheme is used for high-speed clock distribution in the transmission line mode (e.g., Multi-Chip Modules), to ensure correct operation, there are several physical constraints . One of the crucial problems is, given a clock net topology with hierarchical buffering, how to redistribute the buffers evenly over the routing plane avoiding congestion, at the expense of wirelength increase. Given a special emphasis to clock buffer redistribution in this paper, our experiments show that on the average congestion is improved by 20% at the cost of a 10% wirelength increase. 3) Finally, a postprocessing step offering a tradeoff between skew and phase-delay is proposed, based on a combination of hierarchical bottom-up geometric matching and bounded radius minimum spanning tree. Previous clock skew minimization techniques did not address those issues simultaneously.