By Topic

Diagnosis and Correction of Logic Design Errors in Digital Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Pi-Yu Chung ; Coordinated Science Lab. and Dept. of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign ; Yi-Min Wang ; Hajj, I.N.

This paper describes a method for the diagnosis and correction of logic design errors in an erroneous gate-level implementation. Our method is robust and covers more types of design errors than previous work. Our major contribution is providing significant improvement in efficiency, which is most crucial for practical applications. The notion of immediate dominator set is introduced for efficient error diagnosis. Implicit enumeration of the function space is developed for achieving fast error correction. Experimental results for a set of ISCAS and MCNC benchmark circuits demonstrate the effectiveness of the proposed techniques. Circuits with thousands of gates can be corrected in minutes.

Published in:

Design Automation, 1993. 30th Conference on

Date of Conference:

14-18 June 1993