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Estimating Architectural Resources and Performance for High-Level Synthesis Applications

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2 Author(s)
A. Sharms ; Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI ; Rajiv Jain

In this paper we present a solution to the following problems related to architectural synthesis. Given an input specification and a perfomance constraint, determine a lower bound number of resources (active and interconnect) required to execute the data flow graph while satisfying the performance constraint. Conversely, determine a lower bound performance for executing an input specification for a given number of resources (active and interconnect). The generated bounds are close to the actual designs synthesized by several existing systems.

Published in:

Design Automation, 1993. 30th Conference on

Date of Conference:

14-18 June 1993