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An incremental zero/integer delay switch-level simulation environment

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1 Author(s)
L. G. Jones ; Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA

Methods used in the implementation of an incremental zero/integer-delay switch-level logic simulator for MOS circuits based on the MOSSIM II switch-level model are presented. Zero-delay timing reduces spurious reevaluations caused by minor changes to signal timing that do not affect logic, while integer-delay timing provides an ability to model race conditions that do affect the logic. The incremental simulator is embedded within a single fully integrated capture-compile-simulate tool. Modifications to the design at any level in the structural design hierarchy are automatically mapped into (possibly many) changes in the underlying transistor netlist and the incremental simulator is triggered to quickly resimulate only the affected regions of the circuit

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:11 ,  Issue: 9 )