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A Memory Efficient Partially Parallel Decoder Architecture for QC-LDPC Codes

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2 Author(s)
Zhongfeng Wang ; Sch. of Electr. & Comput. Sci., Oregon State Univ., Corvallis, OR ; Zhiqiang Cui

In this paper, a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check codes using (modified) min-sum decoding algorithm is proposed. In general, more than thirty percent of memory can be saved over conventional partially parallel decoder architectures. To reduce the computation delay of check-node processing unit, an efficient architecture based on variants of rank order filter is presented. The optimized partially parallel decoder architecture can linearly increase the decoding throughput with small hardware overhead. Consequently, the proposed approach facilitates the applications of LDPC codes in area/power sensitive high speed communication systems

Published in:

Signals, Systems and Computers, 2005. Conference Record of the Thirty-Ninth Asilomar Conference on

Date of Conference:

Oct. 28 2005-Nov. 1 2005