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A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme

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6 Author(s)
Shibata, N. ; NTT Electron. Corp., Machida, Japan ; Kiya, H. ; Kurita, S. ; Okamoto, H.
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Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-Vth MOSFETs has a high operating speed, while a low-leakage power switch with a high-Vth MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-Vth and low-Vth MOSFETs (that is, multi-Vth CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V. In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word × 8-bit SRAM chip, fabricated with the 0.35-μm multi-Vth CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 μW and that for 25-MHz operation is 1 mW, excluding that of the I/O buffers.

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Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 3 )