By Topic

90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Yamaoka, M. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Maeda, N. ; Shinozaki, Y. ; Shimazaki, Y.
more authors

The power consumption of a low-power system-on-a-chip (SoC) has a large impact on the battery life of mobile appliances. General SoCs have large on-chip SRAMs, which consume a large proportion of the whole LSI power. To achieve a low-power SoC, we have developed embedded SRAM modules, which use some low-power SRAM techniques. One technique involves expanding the write margin; another is a power-line-floating write technique, which enables low-voltage write operation. The power-line-floating write technique makes it possible to lower the minimum operating supply voltage by 100 mV. The other techniques involve using a process-variation-adaptive write replica circuit and reducing leakage current. These techniques reduce active power during write operations by 18% and reduce active leakage of the word-line driver by 64%. The prototype SRAM modules achieve 0.8-V operation, and a 512-kb SRAM module achieves 48.4-μA active leakage and 7.8-μA standby leakage with worst-leakage devices.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 3 )