By Topic

MATIA: a programmable 80 μW/frame CMOS block matrix transform imager architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Bandyopadhyay, A. ; Analog Devices Inc., Wilmington, MA, USA ; Jungwon Lee ; Robucci, R.W. ; Hasler, P.

In this paper, we introduce our CMOS block MAtrix Transform Imager Architecture (MATIA). This imager is capable of performing programmable matrix operations on an image. The imager architecture is both modular and programmable. The pixel used in this architecture performs matrix multiplication while maintaining a high fill factor (46%), comparable to active pixel sensors. Floating gates are used to store the arbitrary matrix coefficients on-chip. The chip operates in the subthreshold domain and thus has low power consumption (80 μW/frame). We present data for different convolutions and block transforms that were implemented using this architecture, and also present data from baseline JPEG and motion JPEG systems which we have implemented using MATIA.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 3 )