A three-data differential signaling over four conductors with pre-emphasis and equalization: a CMOS current mode implementation

A current-mode differential signaling of three data over two pairs of transmission lines increases the effective maximum data rate per pair of transmission lines by about 37% over the conventional pure differential signaling. Each of two data is transmitted as a half-swing differential signal over a pair of transmission lines. The third data is transmitted as a half-swing complementary common-mode signal of the two pairs of transmission lines. Both a single-tap pre-emphasis and a single-tap decision feedback equalizer are combined with this work. Adding a D flip-flop between the equalizer amplifier and the MUX embedded D flip-flop of receiver enables 4-Gb/s operation of receiver. The chip fabricated by using a 0.25-/spl mu/m CMOS process shows the maximum data rates of 4 and 3.2 Gb/s over 20- and 60-cm-long FR4 transmission lines, respectively, with bit-error rate below 1E-12.