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A CMOS low-power mixed-signal clock and data recovery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR backplane transceiver, and consists of a phase detector, loop filter, phase control logic, and phase interpolator. A unique subsampled architecture makes it possible for a low-power mixed-signal clock recovery loop running at a rate of 6 Gb/s. The proposed architecture has data pattern independent loop bandwidth. Fabricated in a 0.13-μm CMOS technology in an area of 280×100 μm2, the clock and data recovery loop exhibits a frequency tracking range up to 2000 ppm. The bit error rate is less than 10-12 with a pseudorandom bit sequence of length 231-1. The power dissipation is 24 mW for clock and data recovery circuits from a single 1.2-V supply.
Date of Publication: March 2006