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A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver

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3 Author(s)
Bo Xia ; Electr. Eng. Dept., Texas A&M Univ., College Station, TX, USA ; A. Valdes-Garcia ; E. Sanchez-Sinencio

This work presents a configurable time-interleaved pipeline architecture as an efficient solution for the ADC design in high data rate multi-standard radios. The ADC is implemented in a 0.25-μm BiCMOS process as part of an integrated dual mode 802.11b/Bluetooth direct conversion receiver. Its structure can be configured to accommodate the different sampling rate and dynamic range requirements of both standards. The different techniques employed at the system and circuit levels to optimize the power consumption are described. An on-line digital calibration scheme is also incorporated to assure the conversion linearity and reduce mismatch among the parallel branches. The proposed ADC is a switched-capacitor implementation occupying an area of 2.1 mm2. It achieves 60 dB/64 dB dynamic range at 44 MHz/11 MHz sampling frequency with a power consumption of 20.2 mW/14.8 mW for the 802.11b/Bluetooth baseband signals.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 3 )