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Metal gate-HfO/sub 2/ MOS structures on GaAs substrate with and without Si interlayer

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11 Author(s)
Ok, Injo ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA ; Kim, Hyoung-Sub ; Manhong Zhang ; Chang-Yong Kang
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In this letter, we studied the effects of post-deposition anneal (PDA) time and Si interface control layer (ICL) on the electrical characteristics of the MOS capacitor with high-/spl kappa/ (HfO/sub 2/) material on GaAs. Thin equivalent oxide thickness (EOT<3 nm) with excellent capacitance-voltage (C-V) characteristics has been obtained. The thickness of the Si ICL and PDA time were correlated with C-V characteristics. It was found that high temperature Si ICL deposition and longer PDA time at 600/spl deg/C improved the C-V shape, leakage current, and especially frequency dispersion (<5%).

Published in:

Electron Device Letters, IEEE  (Volume:27 ,  Issue: 3 )