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This paper describes the detail design considerations and verification of a 10 Gb/s half-rate clock and data recovery circuit (CDR). This CDR circuit utilizes half-rate bang-bang architecture with additional frequency acquisition loop to ensure proper operation and avoid false locking. Direct bang-bang frequency tuning is applied to eliminate the latency of the charge pump and allow flexible control of the small bang-bang frequency tuning step. The CDR circuit was fabricated in TSMC 0.13 μm RF/MS CMOS technology. Experimental results show 1.4 ps rms jitter and 7 ps peak-to-peak jitter generation by 231-1 PRBS at a rate of 10 Gb/s. Jitter transfer bandwidth is about 8 MHz and jitter tolerance has large margin above OC-192 mask. The circuit excluding the output buffers dissipates 86 mW power at 1.5 V power supply. The die size including the pads is 1.3×1.5 mm2.