Ultra low-power radio design for wireless sensor networks

Power consumption and size are the most important challenges faced when designing radios for distributed wireless sensor networks (WSN). Reducing power consumption requires optimization across all the layers of the communication systems. Although the MAC layer plays a crucial role in the overall energy efficiency, the radio remains one of the bottleneck for implementing ultra low-power WSN. The power consumption of the radios available today does not allow for continuous operation and the radio has to be duty-cycled in order to reach the targeted several years autonomy. This clearly has an impact on how to design a radio for WSN. Reducing the node size can be partly achieved by a high level of integration of all the functions required by one node on a single chip. This leads to systems-on-chip (SoC) that are dedicated to WSN. This paper addresses the different issues in the design of ultra low-power WSN with a particular emphasis on the radio. It reviews the constraints imposed on the transceiver design by the low-power and low-voltage specifications, the duty-cycled operation and the modulation scheme. Several radio architectures that can potentially be used for WSN are discussed in the perspective of a CMOS implementation. As examples, the 1st-and 2nd-generation of WiseNET ultra low-power transceivers are presented. The 1st-generation WiseNET transceiver is integrated in a 0.5 /spl mu/m standard digital CMOS process. It operates in the 434 MHz band and consumes only 1 mW from a 1 V supply, while achieving a -95 dBm sensitivity for a 24 kb/s data rate with a 10/sup -3/ BER. The 2nd-generation WiseNET transceiver was designed and specifically optimized for the new WiseMAC protocol specially developed for WSN. It runs from a single 1.5 V battery and operates down to 0.9 V while consuming only 1.8 mW in receive mode. It achieves a -104 dBm sensitivity for 25 kb/s data rate with a 10/sup -3/ BER. In addition to this low-power radio, the 2nd-generation WiseNET system-on-chip (SoC) also includes all the functions required for data acquisition, processing and storage of the information provided by the sensor. The WiseNET solution comprising the WiseNET SoC together with the WiseMAC protocol consumes more than 30 times less power than comparable solutions available today, using for example the IEEE 802.15.4 standard. Finally, some important blocks such as the frequency synthesizer and the ADC are discussed in the perspective of moving to higher data rates, higher operating frequency and phase modulation, taking as example the IEEE 802.15.4 standard. Examples of injection locked oscillators and dividers are given. The conversion of I/Q phase modulated signals to digital are illustrated by an example of an I/Q /spl Delta/-/spl Sigma/ ADC and a direct phase ADC.