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This paper focuses on the features and evaluation of the processor board architecture of MARS with special emphasis on Lisp processing. Inside the processor board, there are four processing units, namely, the instruction fetch unit (IFU), integer processing unit (IPU), floating-point processing unit (FPU) and list processing unit (LPU). The IFU feeds instructions to the processing units and supports the branch handling mechanism to reduce branch penalty; the IPU handles integer operations, string manipulation, and operand address calculations; the FPU deals with the floating point data type, which conforms to IEEE standard 754; and the LPU manages Lisp runtime environment, tag operation, dynamic type checking, and list access. In this architecture, not only new tagged representation of list suitable for RISC operation is proposed, but multiple processing units to separate the execution of complex register file and an ALU operation would relieve the timing constraint. Also, by using a branch control mechanism (called branch peephole) combined with hardware and software techniques to handle the control transfer, this architecture can achieve zero delay branch and zero cycle jump. Simulation results show that, with 50 ns cycle time, MARS will greatly outperform MIPS-X, SPUR, and symbolics 3600.