Scheduled System Maintenance:
On Wednesday, July 29th, IEEE Xplore will undergo scheduled maintenance from 7:00-9:00 AM ET (11:00-13:00 UTC). During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Universal architecture for matrix transposition

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Panchanathan, S. ; Dept. of Electr. Eng., Ottawa Univ., Ont., Canada

A new real-time architecture for matrix transposition is presented. This architecture exploits the inherent parallelism and pipelining of the transposition operation resulting in an efficient mapping of the operation (algorithm) onto the structure. More importantly, this architecture is a universal implementation of executing matrix transposition because it allows data to flow in and out of the structure in either serial or parallel fashion. This architecture has potentially wide applications in real-time data processing, particularly in the areas of signal processing, FFT computations, multidimensional image processing, robotic-vision, database manipulation etc. A basic cell is defined which represents a matrix element and is capable of handling data K bits in width. For a N*N matrix, N2 basic cells are connected in a pipelined fashion along the N rows (N columns) of the matrix with the interconnection between adjacent rows (columns) organised in a serpentine fashion. The architecture has a very small execution time and low communication complexity. The simplicity and regular nature of the structure combined with the local interconnection of the elements makes VLSI implementation of the architecture possible.

Published in:

Computers and Digital Techniques, IEE Proceedings E  (Volume:139 ,  Issue: 5 )