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The study of silicon dies stress in stacked die packages

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4 Author(s)
Yamada, E. ; Texas Instruments Japan Ltd., Ibaraki, Japan ; Abe, K. ; Suzuki, Y. ; Amagai, M.

The purpose of the present study is to understand the overhang size effect of stacked die package on a chip. The deflection and stress in the chip as during wire bonding is evaluated using finite element model. It is considered that stresses in the part of top die over the spacer edge, and effect of the thickness on the chip is discussed. Also, this study provides stresses of the structure around a bond pad during bonding process. The stress of a top die is investigated for two types of spacer materials, silicon and resin spacer, respectively.

Published in:

Electronics Materials and Packaging, 2005. EMAP 2005. International Symposium on

Date of Conference:

11-14 Dec. 2005