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Semiconductor integrated circuit packaging technology challenges - next five years

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1 Author(s)
M. A. Bolanos ; Texas Instruments Inc., Dallas, TX, USA

This paper addresses many of the IC packaging technology challenges that need to be addressed during the next five years. This is the era of communications. consumer products are driving the majority of the electronics industry growth in the next decade; these products generally prioritize power over performance. Electronic products used in automotive applications are also showing steady growth rate. This trend combined with the proliferation of other electronic end equipments has resulted in a large diversity of new IC package types, each designed to meet a specific application or market. The introduction of advanced CMOS processes, with copper interconnect and ultra-low-k dielectrics, is also presenting major challenges from a silicon-packaging integration perspective. This is resulting in new requirements for up-front development and collaboration between package engineers and IC process development organizations. The emergence of system on chip, SoC, and system in package, SiP, is driving more complexity, functionality, and heterogeneous technology integration. Power has become a key technology hurdle, both at the silicon level, as well as at the packaging and system level. Thermal challenges are driving non traditional thermal management solutions. The increased complexity in many of these package families, combined with reduced time to market requirements, has created a need for automated package and chip co-design methodologies to achieve optimum electrical and mechanical reliability performance in final products.

Published in:

2005 International Symposium on Electronics Materials and Packaging

Date of Conference:

11-14 Dec. 2005