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In this brief, we demonstrate that ultralow-loss and broadband inductors can be obtained by using the CMOS process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the inductors. The results show that a 378.5% increase in maximum Q-factor (Qmax) (from 10.7 at 4.7 GHz to 51.2 at 14.9 GHz), a 22.1% increase in self-resonant frequency (fSR) (from 16.5 to 20.15 GHz), a 16.3% increase (from 0.86 to 0.9999) in maximum available power gain (GAmax) at 5 GHz, and a 0.654-dB reduction (from 0.654 dB to 4.08×10-4 dB) in minimum noise figure (NFmin) at 5 GHz were achieved for a 2-nH inductor after the backside ICP dry etching. In addition, state-of-the-art ultralow-loss GAmax≤0.99 (i.e., NFmin≤0.045 dB) for frequencies lower than 12.5 GHz was achieved for this 2-nH inductor after the backside inductively coupled-plasma dry etching. This means this on-chip inductor-on-air can be used to realize an ultralow-noise 3.1-10.6 GHz ultrawide-band RFIC. These results show that the CMOS process compatible backside ICP etching technique is very promising for system-on-a-chip applications.