High-level synthesis of /spl Delta//spl Sigma/ Modulator topologies optimized for complexity, sensitivity, and power consumption

This paper proposes a novel topology-synthesis methodology for single-loop single-bit /spl Delta//spl Sigma/ modulators. The goal is to explore all possible topologies and to obtain the optimal topology under various design considerations, such as hardware complexity, modulator sensitivity, and power consumption. A generic modulator architecture that incorporates all possible feedback and feedforward signal paths was defined and the symbolic noise transfer function (NTF) and signal transfer function (STF) for the generic topology were derived. The symbolic functions were then used to formulate the topology-exploration problem as a mixed-integer nonlinearly constrained programming (MINLP) problem that simultaneously generates and selects the optimal modulator topology with respect to the cost function. Experiments show the superiority of synthesized topologies as compared to traditional modulator topologies.