Cart (Loading....) | Create Account
Close category search window
 

A dynamic routing mechanism for network on chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ali, M. ; Inst. of Comput. Sci., Innsbruck Univ., Austria ; Michael Welzl ; Hellebrand, S.

With an increase in the number of transistors on-chip, the complexity of the system also increases. In order to cope with the growing interconnect infrastructure, the "network on chip (NoC)" concept was introduced. With network methodologies coming on-chip, various characteristics of traditional networks come into play. So far, failures that are common in regular networks were hardly considered on-chip; this paper introduces ideas of dynamic routing in the context of NoCs and explains how they could be applied to cope with adverse physical effects of deep submicron technology.

Published in:

NORCHIP Conference, 2005. 23rd

Date of Conference:

21-22 Nov. 2005

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.